By Topic

Formulating SoC test scheduling as a network transportation problem

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

1 Author(s)
Koranne, S. ; Tanner Res. Inc., Pasadena, CA, USA

A formulation of core-based system-on-chip (SoC) test scheduling as a network transportation problem is presented. Given a set of tests, with demands for transportation of test bits (either for test stimuli or test response) and unrelated parallel test resources (e.g., test access mechanisms or built-in self-test engines), the authors determine the start times and resource mappings of all the tests such that the finish time for the complete SoC test is minimized. The problem is NP-hard and they present an approximation algorithm using a result from the solution of the single source unsplittable flow problem. The proposed method uses the number of test bits that need to be transported for a test as the invariant and is hence relatively independent of the test application and execution model. Experimental results on benchmark SoCs demonstrate that their method outperforms the state-of-the-art integer linear programming formulations, not only in terms of schedule quality, but also significantly reduces the computation time.

Published in:

Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on  (Volume:21 ,  Issue: 12 )