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Failure mechanism of power DMOS transistors under UIS stress conditions

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4 Author(s)
A. Icaza-Deckelmann ; Inst. for Phys. of Electrotechnol., Tech. Univ. Munich, Germany ; G. Wachutka ; J. Krumrey ; F. Hirler

The failure mechanism of multiple-cell power DMOS transistors under UIS stress conditions, where the device current is imposed by the external circuit, is investigated by means of electrothermal device simulation. The results suggest that the failure is caused by the concentration of the each cell's current in a bipolar transistor structure. In the simulation, a strong temperature rise precedes this pattern formation, within application-relevant current levels. Our analysis shows that the heat generated by the high current density may lead to an instability, and that subsequently the device current is likely to concentrate in one single cell of the device, producing eventual failure.

Published in:

Advanced Semiconductor Devices and Microsystems, 2002. The Fourth International Conference on

Date of Conference:

14-16 Oct. 2002