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A single-chip U-interface transceiver for ISDN

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6 Author(s)

The authors discuss system and implementation aspects of a 144 kbit/s one-chip U-transceiver based on echo-cancellation techniques using the MMS43 line code and a Barker synchronization word for bit and frame timing, and including a 1-kb/s transparent channel for maintenance purposes. The LSI is realized by a 2-μm CMOS, double-metal, double-poly technology shrinkable to a 1.5-μm technology and packaged in a 28-pin DIL (dual in-line) package.

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:22 ,  Issue: 6 )

Date of Publication:

Dec 1987

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