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The architecture, design, and performance of a filter implemented in CCD/NMOS technology is described. The device features programmability of the reference signal, the filter length, and weighting coefficient resolution. Off-chip circuitry is minimized by incorporating both analog and digital support circuitry, such as clock logic, drivers, amplifiers, and microprocessor interface circuitry on chip. This results in a monolithic analog signal processing system that has the flexibility to be operated in nine programmable configurations, from 1024 stages by 1 bit, to 128 stages by 8 bits. The versatility of the device makes it suitable for a wide range of applications, from matched filtering with chirp signals and very long binary sequences, to image correlation and chirp signals and very long binary sequences, to image correlation and programmable filtering.