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A novel bipolar RAM cell is introduced, which combines low standby power with high-speed read and write capability. In the standby mode, the operation is entirely static at a power level of less than 1 /spl mu/W/cell. Read and write selection are performed by an increase of cell current, while discrimination is based on the fact that a cell is selected during only a certain period of time. Investigations on exploratory chips containing 4/spl times/1 arrays have demonstrated the feasibility of large arrays, and have shown a minimum read delay of 12 ns, when a sense voltage of 200 mV difference between the bit lines is used. Improvements in cell layout have led to a unit cell area of 2750 /spl mu/m/SUP 2/ using 5 /spl mu/m design rules, which would enable the realization of a 4 kbit RAM on a 15 mm/SUP 2/ chip. Read access and cycle time for this RAM are predicted to be 65 ns and 160 ns, respectively, at a peak power dissipation of 50 mW.