Skip to Main Content
An open-loop, JFET input, high-speed buffer, designed without feedback, is described. Careful biasing of source and emitter followers ensures accurate unity gain and gain linearity with 10 mA of load current. A unique quasi-quad input FET layout provides excellent matching and thermal gradient cancellation and simultaneously optimizes speed performance. Offset voltage is permanently adjusted at wafer test by Zener-zap trimming. The output is capable of driving large capacitive loads with 70 mA of peak current.