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Describes the design and implementation of a 44 Mbit/s serial pipeline multiplier that exploits an efficient algorithm with a novel circuit architecture. The multiplier, intended for use with signed-magnitude coefficients and two's complement data of arbitrary length, produces products automatically rounded and truncated to the same length as incoming data. The circuit's design focuses on the bit-cell, a unit of circuitry associated with one bit of the coefficient word, from which multipliers of arbitrary complexity may be constructed. A practical realization of this multiplier contains four bit-cells, each of which dissipates 20 mW, as well as all associated data, coefficient, and control registers necessary for its operation. The total power dissipation for the chip is 140 mW. The physical implementation of the multiplier employs buried-collector bipolar devices and two-level aluminum metallization to obtain a compact chip 120 mil/SUP 2/. Descriptions of the circuit's arithmetic architecture, design, performance, and use are given in detail.
Date of Publication: June 1978