An integrated test concept for switched-capacitor dynamic MOS RAM's

An approach to dynamic MOS RAM testing has been developed. This paper deals in particular with the test problems of switched-capacitor (or single-transistor) MOS RAMs. Test procedures are developed from an understanding of the technology with which the memory circuits are built. The associated design weaknesses and failure modes are first reviewed, and four simple pattern-sensitivity programs are generated. Finally, an efficient test flow is recommended for rigorous functional verification as well as design and yield improvements.