By Topic

Synthesis of single-output space compactors for scan-based sequential circuits

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
Bhattacharya, B.B. ; ACM Unit, Indian Stat. Inst., Calcutta, India ; Dmitriev, A. ; Gossel, M. ; Chakrabarty, K.

This paper addresses the problem of space compaction of test responses of combinational and scan-based sequential circuits. In a general circuit, compaction of output space to a single output with zero-aliasing cannot always be achieved by earlier known approaches. In this work, it is shown that given a precomputed test set T, the test responses at the functional outputs of any arbitrary circuit-under-test (CUT) can be compacted to a single periodic output, with guaranteed zero aliasing. All the errors that are produced by T at the outputs of the CUT will also appear at the output of the compactor. The method is independent of the fault model and the structure of the CUT and uses only the knowledge of the test set T and the corresponding fault-free responses. A new concept of distinguishing outputs and a characteristic function is used to design the compactor. The test vectors in T are appropriately ordered to optimize the compactor logic, which to achieve zero-aliasing uses a test pattern counter to designate the sequence of test application and a special code checker. A design procedure is described to synthesize the compactor using logic synthesis tools, and relevant experimental results on hardware overhead for several benchmark circuits are presented. It is further shown that the overhead can be significantly reduced if the constraint of exact zero aliasing is slightly relaxed.

Published in:

Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on  (Volume:21 ,  Issue: 10 )