A circuit design to suppress asymmetrical characteristics in 16-Mbit DRAM sense amplifier

Recently, l6-Mbit DRAMS have been designed and fabricated using submicron CMOS technology. However, the submicron MOSFETs with LDD or Efficient Punch through Stop (EPS) structure 111 have serious problems-such as 1) the drain current asymmetry, 2) the threshold voltage difference , and 3) the gate/source capacitance imbalance.