A video frequency bit-parallel CMOS FIR median hybrid filter

Fast pipelined implementation of the FE Median Hybrid filter has been designed on CMOS. The filter structure combines linear averaging subfilters to a median operation in a way that leads to a very efficient implementation. The filter removes noise while preserving sharp edges in the signals. The integrated circuit can operate up to SOME. clock rates and it is capable of 5ltving real time video signals including future HDTV applications. The window size is adjustable from S to 257 samples.