By Topic

Stress analysis and design optimization of a wafer-level CSP by FEM simulations and experiments

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

5 Author(s)
Rzepka, S. ; Dept. of Electr. Eng., Dresden Univ. of Technol., Germany ; Hofer, E. ; Simon, E. ; Meusel, E.
more authors

A design assessment and optimization process for wafer-level chip size packages (WLCSP) is demonstrated. Besides the basic design, the thermal stress in WLCSPs with underfill and with increased standoff height, respectively, are analyzed by finite element method (FEM) simulations. The results are validated and a lifetime model is calibrated by experiments. Also, a WLCSP with stacked balls is optimized using the FEM models. Its total gain in lifetime over the basic design is estimated to reach 780%. WLCSP with optimum underfill endure 10 to 20 times longer than the basic WLCSPs. Soft underfill, however, has almost no effect on the critical inelastic strain. In addition to these practical results, the paper discusses some of the risks of FEM models (such as the singularity problem) and proposes ways of avoiding or overcoming them.

Published in:

Electronics Packaging Manufacturing, IEEE Transactions on  (Volume:25 ,  Issue: 2 )