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A binocular CMOS range image sensor with bit-serial block-parallel interface using cyclic pipelined ADCs

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6 Author(s)
T. Kato ; Yamatake Corp., Kanagawa, Japan ; S. Kawahito ; K. Kobayashi ; H. Sasaki
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A binocular CMOS image sensor used with a pair of aligned-in-parallel optical systems for range imaging is implemented. Sixteen compact cyclic pipelined analog-to-digital converters are integrated per an image sensor. The dedicated processor starts 16/spl times/16 FFT when the first bit-serial block-parallel data is obtained. The image sensor produces a 16/spl times/16 range image from a pair of 256/spl times/256 images, together with the dedicated pipelined FFT processor, at the maximum pipeline performance.

Published in:

VLSI Circuits Digest of Technical Papers, 2002. Symposium on

Date of Conference:

13-15 June 2002