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A new architecture of programmable digital vision chip

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3 Author(s)
Komuro, T. ; Dept. of Inf. Phys. & Comput., Univ. of Tokyo, Japan ; Kagami, S. ; Ishikawa, M.

In this paper we propose a new architecture of digital vision chip, in which photo detectors and parallel processing elements designed in digital circuits are integrated together. In this architecture, the function to join several PEs is introduced and summation is calculated at high speed. Also, some sample algorithms and a 64/spl times/64 pixels prototype chip we developed will be described.

Published in:

VLSI Circuits Digest of Technical Papers, 2002. Symposium on

Date of Conference:

13-15 June 2002