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Enabling high-performance mixed-signal system-on-a-chip (SoC) in high performance logic CMOS technology

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13 Author(s)
Franca-Neto, L.M. ; Intel Labs, Hillsboro, OR, USA ; Pardy, P. ; Ly, M.P. ; Rangel, R.
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Presents a technique to enable the integration of sensitive analog circuits with a Pentium class microprocessor, on a lossy substrate that sees 190 mVrms of equivalent noise at the center of the die. Measurement results of substrate noise on a Pentium 4/spl reg/ 1 GHz processor show that we can exploit the spectral content of this noise, and use appropriately tuned analog amplification to limit the isolation requirements to 70 dB. By using a combination of measurement and field solver results, we show that a minimal process enhancement (i.e. a deep nwell) will yield 50 dB of isolation. We use measured mismatch data and analysis to conclude that the remaining 20 dB can be achieved by symmetric matched layouts and fully differential circuit topologies. We describe two deep nwell biasing techniques (substrate noise trapping and floating deep nwell) to realize the 50 dB on-die isolation. Finally, we use measurements to show that the deep nwell does not adversely impact the high frequency performance of 140 nm logic CMOS devices.

Published in:

VLSI Circuits Digest of Technical Papers, 2002. Symposium on

Date of Conference:

13-15 June 2002