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SESO memory: a CMOS compatible high density embedded memory technology for mobile applications

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6 Author(s)
Atwood, B. ; Central Res. Lab., Hitachi Ltd., Tokyo, Japan ; Ishii, T. ; Osabe, T. ; Mine, T.
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SESO memory is proposed as a high density, low power embedded memory. Based on an ultra-low leakage thin-film transistor fabricated with standard CMOS logic techniques, this embedded memory has a density almost three times larger than SRAM and requires no additional processing materials. Fabricated SESO transistor characteristics are presented and a 3-transistor cell structure is analyzed, showing SESO memory to be a strong candidate as an inexpensive embedded memory.

Published in:

VLSI Circuits Digest of Technical Papers, 2002. Symposium on

Date of Conference:

13-15 June 2002