Referenced Items are not available for this document.
A clock and data recovery (CDR) circuit using multi phase gated VCO (MGVCO) technique for multi-channel high-speed serial interface was developed. This architecture can realize quick data acquisition and plesiochronous clocking capability. A 5 Gbps 32-channel test chip, designed in 0.18 /spl mu/m CMOS technology, achieved BER of <10/sup -12/ in 5 Gbps CDR operation with /spl plusmn/3% frequency tolerance for random incoming data of 2/sup 7/-1.
Published in:
VLSI Circuits Digest of Technical Papers, 2002. Symposium on
Date of Conference: 13-15 June 2002
- Page(s):
- 82 - 83
- Print ISBN:
- 0-7803-7310-3
- INSPEC Accession Number:
- 7432194
- Conference Location :
- Honolulu, HI, USA
- Digital Object Identifier :
- 10.1109/VLSIC.2002.1015052
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