Referenced Items are not available for this document.
BLR is incorporated into a L1 cache design in a 100 nm dual-V/sub T/ technology to eliminate impacts of bitline leakage on performance and noise margin with minimal area overhead. Bitline delay is 23% better than the best conventional design, thus enabling 6 GHz operation at with 15% higher energy.
Published in:
VLSI Circuits Digest of Technical Papers, 2002. Symposium on
Date of Conference: 13-15 June 2002
- Page(s):
- 50 - 51
- Print ISBN:
- 0-7803-7310-3
- INSPEC Accession Number:
- 7432190
- Conference Location :
- Honolulu, HI, USA
- Digital Object Identifier :
- 10.1109/VLSIC.2002.1015042
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