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A 6 GHz, 16 Kbytes L1 cache in a 100 nm dual-V/sub T/ technology using a bitline leakage reduction (BLR) technique

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5 Author(s)
Yibin Ye ; Microprocessor Res., Intel Labs, Hillsboro, OR, USA ; M. Khellah ; D. Somasekhar ; A. Farhang
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BLR is incorporated into a L1 cache design in a 100 nm dual-V/sub T/ technology to eliminate impacts of bitline leakage on performance and noise margin with minimal area overhead. Bitline delay is 23% better than the best conventional design, thus enabling 6 GHz operation at with 15% higher energy.

Published in:

VLSI Circuits Digest of Technical Papers, 2002. Symposium on

Date of Conference:

13-15 June 2002