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A 4.5 GHz 130 nm 32 KB L0 cache with a self reverse bias scheme

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6 Author(s)
Hsu, S.K. ; Intel Labs, Intel Corp., Hillsboro, OR, USA ; Alvandpour, A. ; Mathew, S. ; Shih-Lien Lu
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This paper describes a 32 KB dual-ported L0 cache for 4.5 GHz operation in 1.2 V, 130 nm CMOS. The local bitline uses a Self Reverse Bias scheme to achieve -220 mV access transistor underdrive without external bias voltage or gate-oxide overstress. 11% faster read delay and 104% higher DC robustness (including 7x measured active leakage reduction) is achieved over optimized high-performance dual-Vt scheme.

Published in:

VLSI Circuits Digest of Technical Papers, 2002. Symposium on

Date of Conference:

13-15 June 2002