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An integrated mixed-signal transceiver for broadband communications is presented. The transceiver includes a configurable dual/single receive data path, a configurable dual/single transmit data path, and auxiliary functions including low-speed ADCs, low-speed DACs, serial port interface, clock and reference generation blocks. The receive data path provides constant input impedance and contains dual input buffers, dual programmable gain stages (PGAs), dual 12-bit ADC blocks, and a digital processing block, all sampling at up to 64 MHz. The transmit data path contains a digital processing block as well, and dual 14-bit DAC blocks with programmable gain, sampling at up to 128 MHz. The chip was implemented in double-poly triple-metal 0.35 /spl mu/m CMOS technology.