By Topic

A novel asymmetric gate recess process for InP HEMTs

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
F. Robin ; Lab. for Electromagn. Fields & Microwave Electron., Swiss Fed. Inst. of Technol., Zurich, Switzerland ; H. Meier ; O. J. Homan ; W. Bachtold

An asymmetric gate recess process has been developed for the fabrication of InP-based HEMTs with improved breakdown voltage. This process is based on a double e-beam exposure of a 4-layers stack of PMGI and PMMA resists. Vertical patterns can be fabricated that can otherwise not be achieved with standard e-beam lithography processes. A 30% improvement of the on-state breakdown voltage of 0.2 μm InP HEMTs was obtained without marked degradation of fmax.

Published in:

Indium Phosphide and Related Materials Conference, 2002. IPRM. 14th

Date of Conference: