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Multirate ΣΔ modulators

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2 Author(s)
Colodro, F. ; Departmento de Ingenieria Electronica, Seville Univ., Spain ; Torralba, A.

New high-speed ΣΔ analog to digital converters (ADCs) are required for xDSL and RF receivers. As sampling frequency is upper limited by the amplifier bandwidth and power consumption, these high-speed, low-power converters operate with a small oversampling ratio. Usually, they are high-order cascade structures with a multibit quantizer in the last stage. All these approaches use a unique sampling frequency. This paper shows that multirating is a useful technique to reduce power consumption in high speed ΣΔ modulators. To this end, two different multirate ΣΔ modulators are proposed. The first one uses a low sampling frequency in the first integrator(s) of a single loop structure, while the second one uses a low oversampling frequency in the first stage(s) of a cascade converter

Published in:

Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on  (Volume:49 ,  Issue: 3 )

Date of Publication:

Mar 2002

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