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In order to improve the productivity of current register transfer level (RTL) design practice, we argue that a new methodology of modeling, simulation and synthesis is needed based on standard RTL semantics. In this paper we present the implementation of a C++ class library for RTL modeling and simulation. This library provides a foundation for experimentation in the new RTL semantics, proposed by Accellera Working Group, which uses FSMD (D.D. Gajski et al, High-Level Synthesis: Introduction to Chip and System Design, Kluwer Academic, 1992) as a formal model of RTL abstraction. The essential C++ classes for modeling FSMD in C++ are described in the paper.