By Topic

Modeling a new RTL semantics in C++

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Zhao, S. ; Center for Embedded Comput. Syst., California Univ., Irvine, CA, USA ; Gajski, D.

In order to improve the productivity of current register transfer level (RTL) design practice, we argue that a new methodology of modeling, simulation and synthesis is needed based on standard RTL semantics. In this paper we present the implementation of a C++ class library for RTL modeling and simulation. This library provides a foundation for experimentation in the new RTL semantics, proposed by Accellera Working Group, which uses FSMD (D.D. Gajski et al, High-Level Synthesis: Introduction to Chip and System Design, Kluwer Academic, 1992) as a formal model of RTL abstraction. The essential C++ classes for modeling FSMD in C++ are described in the paper.

Published in:

Circuits and Systems, 2002. ISCAS 2002. IEEE International Symposium on  (Volume:5 )

Date of Conference: