By Topic

A low-power subscriber line interface circuit in a high-voltage CMOS technology

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
M. Vahidfar ; Dept. of Electr. Eng., Sharif Univ. of Technol., Tehran, Iran ; A. Tajalli ; M. Atarodi

A low-power CMOS Subscriber Line Interface Circuit (SLIC) in a 1 μm high voltage technology is presented. A systematic approach to extract the necessary specification for each block to achieve stability, accuracy, and other desired SLIC characteristics is applied. For this purpose a proper sense and feed system is introduced. The proposed SLIC shows a longitudinal balance of 53.7 dB while consumes 2.5 mA current with 16 mm2 area. This transformer-less SLIC met transmission specifications without trimming.

Published in:

Circuits and Systems, 2002. ISCAS 2002. IEEE International Symposium on  (Volume:5 )

Date of Conference: