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Hardware optimized direct digital frequency synthesizer architecture with 60 dBc spectral purity

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2 Author(s)
J. M. P. Langlois ; Dept. of Electr. & Comput. Eng., R. Mil. Coll. of Canada, Kingston, Ont., Canada ; D. Al-Khalili

We introduce a novel sine-output Direct Digital Frequency Synthesizer (DDFS) architecture, optimized for hardware implementation, that achieves better than 60 dBc spectral purity from DC to the Nyquist frequency. Instead of a ROM, we use a hardware efficient phase-to-sine amplitude converter that approximates the first quadrant of the sine function with eight equal length piecewise linear segments. The converter's complexity is significantly reduced through careful selection of the segments' slopes and y-intercepts. The description of the synthesizer in VHDL requires less than 200 lines of code, and implementation in a X4000 series FPGA requires only 59 configurable logic blocks. The architecture is particularly suitable for low power wireless communications applications.

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Circuits and Systems, 2002. ISCAS 2002. IEEE International Symposium on  (Volume:5 )

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