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A low-power, low-noise CMOS amplifier for neural recording applications

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1 Author(s)
Harrison, R.R. ; Dept. of Electr. & Comput. Eng., Utah Univ., Salt Lake City, UT, USA

There is a need among scientists and clinicians for low-noise, low-power biosignal amplifiers capable of amplifying signals in the mHz to kHz range while rejecting large dc offsets generated at the electrode-tissue interface. The advent of fully-implantable multielectrode arrays has created the need for fully-integrated micropower amplifiers. We designed and tested a novel bioamplifier that uses a MOS-bipolar pseudo-resistor to amplify signals down to the mHz range while rejecting large dc offsets. We derive the theoretical noise-power tradeoff limit - the noise efficiency factor - for this amplifier and demonstrate that our VLSI implementation approaches that limit. The resulting amplifier, built in a standard 1.5μm CMOS process, passes signals from 0.1mHz to 7.2kHz with an input-referred noise of 2.2μVrms and a power dissipation of 80μW while consuming 0.16mm2 of chip area.

Published in:

Circuits and Systems, 2002. ISCAS 2002. IEEE International Symposium on  (Volume:5 )

Date of Conference:

2002