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RNS realization of fast fixed-point multipliers with large wordlengths

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3 Author(s)
G. C. Cardarilli ; Dept. of Electr. Eng., Rome Univ., Italy ; R. Lojacono ; M. Salerno

The application of the residue number system (RNS) to signal processors has been widespread. In the case of infinite impulse response (IIR) digital filters, the application of the method implies the continuous scaling of the results, as in the case of autoscale multipliers. A different method of applying the RNS technique to fixed-point arithmetics was previously proposed by the authors. For this purpose, two finite arithmetics defined with respect to two different moduli were used. A case of particular interest was considered, i.e. that of 8-bit arithmetic, in which a limited amount of memory is needed to store the isomorphism tables. An extension of the above algorithm to the case of higher dynamic ranges is considered. The approach uses a radix-p representation and requires the same isomorphism tables already defined in the case of 8-b arithmetics. The algorithm thus preserves the memory requirements. If p=128 and the wordlength is 7L+1, the 8-b processor can be used as an elementary building block of the whole multiplying structure. A 22-b multiplier is considered in detail and compared to the traditional ones with respect to the time and area requirements for a VLSI realization

Published in:

Circuits and Systems, 1989., IEEE International Symposium on

Date of Conference:

8-11 May 1989