By Topic

A manufacturable shallow trench isolation process for sub-0.2 um DRAM technologies

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

11 Author(s)
Lien, W.Y. ; R&D, Taiwan Semicond. Manuf. Co., Hsin-Chu, Taiwan ; Yeh, W.G. ; Li, C.H. ; Tu, K.C.
more authors

A highly manufacturable and defect-free shallow trench isolation (STI) process is demonstrated by using 64M DRAM as a sensitive monitor. In the STI flow, a special sequence of extra anneal (1100C) after corner oxidation (i.e., liner oxide) and an RTA (1000C) anneal after HDP CVD oxide deposition can result in a significantly higher yield in 64M DRAM by effectively reducing silicon stress related substrate defects.

Published in:

Advanced Semiconductor Manufacturing 2002 IEEE/SEMI Conference and Workshop

Date of Conference:

2002