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A manufacturable shallow trench isolation process for sub-0.2 um DRAM technologies

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11 Author(s)
W. Y. Lien ; R&D, Taiwan Semicond. Manuf. Co., Hsin-Chu, Taiwan ; W. G. Yeh ; C. H. Li ; K. C. Tu
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A highly manufacturable and defect-free shallow trench isolation (STI) process is demonstrated by using 64M DRAM as a sensitive monitor. In the STI flow, a special sequence of extra anneal (1100C) after corner oxidation (i.e., liner oxide) and an RTA (1000C) anneal after HDP CVD oxide deposition can result in a significantly higher yield in 64M DRAM by effectively reducing silicon stress related substrate defects.

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Advanced Semiconductor Manufacturing 2002 IEEE/SEMI Conference and Workshop

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