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SPA - a synthesisable Amulet core for smartcard applications

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6 Author(s)
L. A. Plana ; Dept. of Comput. Sci., Manchester Univ., UK ; P. A. Riocreux ; W. J. Bainbridge ; A. Bardsley
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SPA is a synthesised, self-timed, ARM-compatible processor core. The use of synthesis was mandated by a need for rapid implementation. This has proved to be very effective, albeit with increased cost in terms of area and performance compared with earlier non-synthesised processors. SPA is employed in an experimental smartcard chip which is being designed to evaluate the applicability of self-timed logic in security-sensitive devices. The Balsa synthesis system is used to generate dual-rail logic with some enhancements to improve security against non-invasive attacks. A complete system-on-chip is being synthesised with a only small amount of hand design being employed to boost the throughput of the on-chip interconnection system.

Published in:

Asynchronous Circuits and Systems, 2002. Proceedings. Eighth International Symposium on

Date of Conference:

8-11 April 2002