A software solution for chip rate processing in CDMA wireless infrastructure

Third-generation cellular infrastructure requires extremely high-performance signal processing in the baseband receiver. Currently, chip rate processing is implemented using FPGA and ASIC technology. The use of a digital signal processor is explored for UTRA FDD systems with the goal of reducing cost and increasing flexibility. By combining chip rate and symbol rate processing within a single platform and taking advantage of the natural capacity of the air interface, load balancing can be performed, which reduces the amount of processing power needed, thereby reducing the cost of the receiver.