A complete strategy for testing an on-chip multiprocessor architecture

The article proposes an approach that divides testing into three phases: router testing, RAM block testing, and distributed processor testing. This test strategy was implemented for the on-chip multiprocessor architecture of a fine-grain, massively parallel machine developed in 1995 at the National Polytechnic Institute of Grenoble. The hierarchical strategy minimizes the entire architecture's test cost by avoiding unnecessary testing. For example, testing a processor that is inaccessible because its router is faulty or that has a faulty local RAM is useless. Furthermore, a fault-free RAM cannot be used if the corresponding node router is faulty.