Scalable parametrizable SMP system core architecture

The levels of scalability and architecture of scalable parametrizable shared memory symmetric multiprocessor (SMP) system core are considered. Proposed scalable parametrizable SMP system architecture is intended for creation ASIC optimised for source algorithm. Based on proposed architecture high-level ASIC synthesis tools are presented. The proposed high-level synthesis tools allow to create custom ASIC which bases on programming language algorithm description.