Test generation for digital device on FPGA, CPLD

The algorithm of test generation based on faults lists cubic cover (FLCC) and single logical path sensitization is offered. The realization of the algorithm is oriented to Field Programable Gate Arrays (FPGAs) up to 200000 gates, including more than 20 types of trigger structures. The projects language description - VHDL, supports the design systems of corporations Aldec and Xilinx.