Analysis of gate-lag phenomena in recessed-gate and buried-gate GaAs MESFETs

Two-dimensional analysis of gate-lag phenomena in recessed-gate and buried-gate GaAs MESFETs is performed, and their dependence on the structural parameters and the off-state gate voltage V/sub Goff/ is studied. It is shown that when V/sub Goff/ is around the threshold voltage (pinchoff voltage) V/sub th/, the gate-lag could be almost eliminated by introducing the buried-gate structure. However, it is suggested that large gate-lag might be seen when V/sub Goff/ is much more negative than V/sub th/.