An ITLDD CMOS process with self-aligned reverse-sequence LDD/channel implantation

An advanced inverse-T LDD (ITLDD) CMOS process has been developed. This process features self-aligned lightly-doped-drain/channel implantation for improved hot-carrier protection. Selective polysilicon deposition is used to define the thick polysilicon gate regions with a thin polysilicon gate regions overlying the lightly doped n/sup -/ and p/sup +/ regions. Since the thick poly gate regions are defined by nitride sidewall spacers, optical lithography can be used to define sub-half-micrometer gate length MOSFETs. The LDD implants are performed after the n/sup +/ and p/sup +/ implants are annealed, resulting in MOSFET's with improved short-channel behavior due to the smaller lateral source/drain diffusion.<
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