An Accurate Process-Induced Variability-Aware Compact Model-Based Circuit Performance Estimation for Design-Technology Co-Optimization

In sub-10-nm fin field-effect transistors (FinFETs), line-edge roughness (LER) and metal-gate granularity (MGG) are the two most dominant sources of variability and are mostly modeled semi-empirically. In this work, compact models of LER and MGG are used. We show an accurate process-induced variability (PIV)-aware compact model-based circuit performance estimation for design-technology co-optimization (DTCO). This work is carried out using an experimentally validated Berkeley Short-channel IGFET Model–Common Multi-Gate (BSIM-CMG) model on a 7-nm FinFET node. First, we have shown performance benchmarking of LER and MGG models with the state of the art and shown
$\sim 4\times $
(
$\sim 2.3\times $
) accuracy improvement for nMOS (pMOS) in the estimation of device figure of merits (DFoMs). Second, ring oscillator (RO) and static random-access memory (SRAM) circuit’s performance estimation is carried out for LER and MGG variability. Furthermore, ~22% more optimistic estimate of (
$\sigma /\mu $
)
_SHM
(static hold margin) compared to the state-of-the-art model with
${V}_{\text {DD}}$
variation is shown. Finally, we demonstrate our improved DFoM accuracy translated to more accurate circuit figure of merits (CFoMs) performance estimation. For worst-case SHM (3(
$\sigma /\mu $
)
_SHM
@
${V}_{\text {DD}}={0.75}$
V) compared to state of the art, dynamic (standby) power reduction by ~73% (~61%) is shown. Thus, our enhanced variability model accuracy enables more credible DTCO with significantly better performance estimates.