A class of systematic t/B-error correcting codes for semiconductor memory systems

This paper proposes a class of systematic codes called single t/B-error correcting - single b-bit byte error correcting - single b-bit block error detecting (S/sub t/B/EC-S/sub b/EC-S/sub B/ED) codes for high speed semiconductor memory systems. The proposed codes correct multiple random t-bit errors occurring within a chip and b-bit byte errors caused by sub-array data faults while simultaneously indicating B-bit block errors caused by complete chip failures.