A CMOS/partial-SOI structure for future ULSIs

An MOS transistor formed partly on lateral epitaxial silicon film on insulator (called the TOLE structure) has been proposed and applied to a DRAM cell. The authors have investigated the potential of the CMOS-TOLE structure for application to future ultra-large-scale integrated circuits (ULSIs). The test CMOS-TOLEs had a 400-nm-thick SiO/sub 2/ film for the SOI insulator, a 100 approximately 200-nm-thick silicon film, and a 20-nm-thick gate oxide. The designed channel width and length for the CMOS-TOLEs measured were 20/2 approximately 2.5 and 6/2 mu m. The bulk part length was 1.2 mu m. The advantages and properties of the structure are discussed. It has been estimated that the necessary storage charge for the CMOS-TOLE DRAM is about 40% of that for the bulk CMOS DRAM and that the typical logic gate delay for the CMOS-TOLE is about 60% of that for the bulk CMOS. Parasitic sidewall channel formation, which is a problem for the n-channel TOLE due to its isolation structure, has been suppressed by channel side impurity control. The leakage current level has been reduced to a value approximately ten times larger than that for the conventional bulk junction.<
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