Testing the printability of VLSI layouts

Lithography has always been a key technology process step for the semiconductor industry. Clearly, both circuit speed and complexity (density) rely on the lithographic minimum printable feature size. For industry, besides pure resolution, throughput is also of paramount importance. For this reason optical lithography has been used ubiquitously for large scale manufacturing, as it guarantees a high wafer throughput. This paper presents an easy to use CAD tool capable of checking whether a VLSI layout can (or not) be correctly printed using a given imaging system. The tool is built upon a layout editor capable of handling phase-shift masks and a lithographic simulator that are tightly integrated.