Design methodology and optimization strategy for dual-V/sub TH/ scheme using commercially available tools

Design methodology for dual-V/sub TH/ scheme using commercially available tools is presented and optimization strategy for the dual-V/sub TH/ scheme is discussed. In order to suppress the power consumption, it is shown that using library cells that have various combinations of V/sub TH/'s is not needed. The cell library, which contains logic gates with all high V/sub TH/ transistors and all low VTH transistors, is sufficient to reduce leakage power. 0.1 V is shown to be the optimum value for V/sub TH/ difference between V/sub TH,HIGH/ and V/sub TH,LOW/ in terms of power reduction.