Fair scheduling of integrated IP and ATM based traffic in 3G mobile communication networks

A flexible platform with the capabilities of handling both real-time IP and ATM traffic enables mobile network operators to offer any combination of 2G and 3G traffic based on IP and ATM. The integration of IP routing and ATM switching into a single network platform provides more efficient and cost-effective use of network resources, dynamically allocating bandwidth in response to changes in the balance of circuit and packet based traffic. This paper presents a hardware-based common scheduling architecture for both IP and ATM traffic in an access node, based on a self-clocked fair queueing (SCFQ) service discipline. The high-speed all parallel matching capability of content-addressable memory (CAM) is used to find the packet or cell with the smallest timestamp (virtual finishing time) destined for a specific output port. Both IP and ATM traffic have their own service classes, and each service class has its own logical queue in our SCFQ architecture. Timestamps of all packets (including ATM cells) are stored in the same CAM array so that fair scheduling of integrated IP and ATM traffic can be achieved.