Manufacturing optimization of shallow trench isolation for advanced CMOS logic technology

As VLSI technologies were scaled below 0.25 /spl mu/m, the semi-recessed thermal oxide (SROX) that was used for device isolation became inadequate. What replaced SROX isolation throughout the industry was pioneered by IBM and is referred to as shallow trench isolation (STI). STI accommodates much smaller design dimensions, but presents new process integration and control challenges. Performance, cost and complexity must be balanced to determine the most effective STI process. This paper discusses process control and manufacturing optimization of IBM's second-generation STI process. Film control details are discussed in the context of process variability. The elimination of several yield-limiting defect mechanisms such as micro-masking and seams is discussed in detail. In addition, corner treatment is discussed along with its impact on actual FET device characteristics.