A 2.5-V 2.0-Gbyte/s 288-Mb packet-based DRAM with enhanced cell efficiency and noise immunity

A 2.5-V 288-Mb packet-based DRAM with 32 banks and 18-DQ organization architecture achieving a peak bandwidth of 2.0-GB/s at V/sub DD/=2.25 V and T=100/spl deg/C has been developed using (1) an area- and performance-efficient chip architecture with a mixture of high-speed interface circuits with DRAM peripheral circuits to increase cell efficiency; (2) a multilevel controlled bitline equalizing scheme and a distributed sense amplifier driving scheme to enhance DRAM core timing margin while increasing the number of cells per wordline for cell efficiency over the previous subwordline driving scheme; (3) a flexible column redundancy scheme with multiple fuse boxes instead of excessive spare memory cell arrays for 143 internal I/O architecture; and (4) optimized I/O circuits and pin parasitic design including pad and package to maximize the operating frequency.