Projecting lifetime of deep submicron MOSFETs

A detailed examination of hot-carrier-induced degradation in MOSFETs from a 0.25-/spl mu/m and a 0.1-/spl mu/m technology is performed. Although the worst case stress condition depends on the stress voltage, channel length, and oxide thickness, I/sub b,peak/ is projected to be the worst case stress condition at the operating voltage for both nMOSFETs and pMOSFETs. Post-metallization anneal (PMA) in deuterium can significantly improve the device lifetime if the primary degradation mechanism at the stress condition is interface trap generation due to interface depassivation by energetic electrons.