High speed re-configurable pipeline ADC cell design

The design and implementation of a high speed reconfigurable pipeline ADC cell is presented in this paper. Each cell in the pipeline can be a sample and hold gain of 1 stage, or gain of 2 as multiplying by 2 stage, or gain of 1.9 stage capable of doing calibration. The design is implemented in TSMC 0.25 /spl mu/m single-poly CMOS digital process.