A VLSI for real-time linear operations and transforms

A VLSI system, utilizing 16 systolic array multipliers, designed to compute vector-matrix products at a rate of 640*10/sup 6/ MACs is presented. The 448,000-transistor, 1.6- mu m CMOS device incorporates a dual timing scheme which allows multiplexing of hardware units over identical operations. This hardware balances maximum internal operating frequency with external data bandwidth and results in an improved ration of the signal throughput to silicon area. This system has wide application because of its ability to compute correlation, convolution, linear transforms, and connections in multilayer perceptrons.<
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