Performance-driven high-level synthesis with bit-level chaining and clock selection

This paper presents a new scheme for scheduling and control synthesis in high-level circuit design. The scheduling algorithm tries to maximize the performance of a design under resource constraints by maximizing the utilization of resources and minimizing clock slack. It exploits the technique of bit-level chaining (BLC) to target high-speed design. It also exploits noninteger multicycling and chaining, which allows multiple cycle execution of a set of chained operations and even sharing of chained functional units to obtain further performance at the cost of a small increase in the complexity of the control unit. Experimental results on several datapath-intensive designs show significant improvement in throughput over the conventional scheduling algorithms.