Design of an equalizer using the DFE structure and the MMA algorithm

This paper proposes an equalizer using MMA (MultiModulus Algorithm) and LMS (Least Mean Square) algorithms and uses a DFE (Decision Feedback Equalizer) structure. The existing MMA equalizer uses two transversal filters but the proposed equalizer uses two DFE filter banks to improve the channel adaptive performance and to reduce the number of taps. The fabricated equalizer ASIC chip using the MMA and LMS algorithms operates at 8 MHz and provides 64 Mbps which is higher than existing equalizers. The chip uses the 0.35 /spl mu/m technology and has about 160000 gates.