Device interfacing: the weakest link in the chain to break into the giga bit domain?

With approaching 1 Gb/s digital I/O buses and I/O margins in the range of 250 ps and less, the signal delivery path becomes increasingly more challenging to manage. Second order effects, systematic errors, and ATE to device interactions, which used to be "noise level " at 100 Mb/s rates, become more and more significant when attempting to make accurate measurements in the Gb/s domain. This paper provides an overview of the challenges, the magnitudes, the associated approaches, and practical methods to address them.