A high IIP2 downconversion mixer using dynamic matching

This paper presents an RF downconversion mixer with improved rejection to second-order intermodulation for RF application within a direct-conversion receiver requiring high input blocking performance. The mixer, implemented in a 2.7-V 0.35-/spl mu/m BiCMOS process, achieves a second-order input intercept point of at least +72 dBm for a BiCMOS design and at least +66 dBm for an all-CMOS design. The design utilizes dynamic matching to enhance the balance of a fully differential mixer through mitigation of both component and device mismatches. In addition, dynamic matching is shown to improve the mixer's 1/f noise performance. For an all-CMOS mixer design, a 30-dB improvement in the mixer's noise floor at 1 kHz has been observed compared to conventional fully differential CMOS Gilbert-cell mixer. Additionally, background is given on second-order intermodulation and on system IIP2 requirements for a direct-conversion receiver.